This invention relates to logic devices employing look up tables, and more particularly to improved ways of providing fast carry functions in such devices when the devices are to be used for such purposes as performing addition, subtraction, and counting.
Programmable logic devices are known in which programmable look up tables are used to perform relatively elementary logic functions (see, for example Wahlstrom U.S. Pat. No. 3,473,160 (FIG. 8) and commonly assigned, co-pending patent application Ser. No. 754,017, filed Sep. 3, 1991). A look up table may provide as an output any desired logical function of several inputs. The outputs of several such look up tables may be combined (e.g., by other similar look up tables) in any desired way to perform much more complex logic functions.
Look up tables which are a good size for performing many elementary logic functions in programmable logic devices tend to be too large for performing the extremely simple functions required to provide two-input adders (including subtracters) and various kinds of counters. For example, four-input look up tables are a very good size for general use, but are larger than necessary for use in the individual binary places of adders and counters. Nevertheless, adders and counters are very often required in digital logic. It is therefore wasteful to use four-input look up tables for adders and counters. This is especially so when fast carry logic is used because for each binary place one four-input look up table is required to provide the sum out bit, and another four-input look table is required to provide the carry out bit. Neither of these look up tables is being fully utilized. Moreover, if large numbers of bit positions or places are required, the need to use two look up tables per bit position may exact a significant speed penalty because of the extensive use which must be made of the interconnect circuitry to interconnect the large number of look up tables involved.
In view of the foregoing, it is an object of this invention to provide improved ways of implementing adders (including subtracters) and counters in programmable logic devices made up of programmable look up tables.
It is a more particular object of this invention to provide programmable logic devices made up of look up tables in which adders and counters can be implemented more efficiently and with less waste of look up table resources.
It is still another more particular object of this invention to provide ways of achieving faster adders and counters in programmable logic devices made up of look up tables.